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Am49LV128BM
Data Sheet
July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.
Publication Number 31022 Revision A
Amendment 6 Issue Date June 17, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
SUPPLEMENT
Am49LV128BM
Stacked Multi-Chip Package (MCP) 128 Megabit (8 M x 16-Bit) MirrorBitTM Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) pseudo-static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES Single power supply operation -- 3 volt read, erase, and program operations Manufactured on 0.23 m MirrorBit process technology SecSiTM (Secured Silicon) Sector region -- 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence -- May be programmed and locked by the customer Flexible sector architecture -- Two hundred fifty-six 32 Kword sectors Compatibility with JEDEC standards -- Provides pinout and software compatibility for singlepower supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125C PERFORMANCE CHARACTERISTICS High performance -- As fast as 105 ns access time -- 25 ns page read times -- 0.5 s typical sector erase time -- 15 s typical write buffer word programming time: 16word write buffer reduces overall programming time for multiple-word updates -- 4-word page read buffer -- 16-word write buffer Low power consumption (typical values at 3.0 V, 5 MHz) -- 30 mA typical active read current -- 50 mA typical erase/program current -- 1 A typical standby mode current Package option -- 64-ball FBGA SOFTWARE & HARDWARE FEATURES Software features -- Program Suspend & Resume: read other sectors before programming operation is completed -- Erase Suspend & Resume: read/program other sectors before an erase operation is completed -- Data# polling & toggle bits provide status -- Unlock Bypass Program command reduces overall multiple-word or byte programming time -- CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features -- Sector Group Protection: hardware-level method of preventing write operations within a sector group -- Temporary Sector Group Unprotect: VID-level method of changing code in locked sector groups -- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects last sector regardless of sector protection settings -- Hardware reset input (RESET#) resets device PSRAM FEATURES Asynchronous SRAM Interface Fast Access Time -- tCE = tAA = 65 ns max Low Voltage Operating Condition -- VDD = 2.7 to + 3.1 V Byte Control by LB# and UB#
Publication Number: 31022_00 Amendment:6
Rev: A
GENERAL DESCRIPTION
The 128 Mbit MirrorBit device is a 128 Mbit, 3.0 volt single power supply flash memory devices organized as 8,388,608 words. The device has a 16-bit wide data bus. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 105 or 110 ns is available. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. Hardware data protection measures include a low V CC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector group to read or program any other sector group and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector group to read any other sector group and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSiTM (Secured Silicon) Sector provides a 128-word area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP#/ACC) feature protects the last sector by asserting a logic low on the WP# pin. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit products, including migration information, data sheets, application notes, and software drivers, please see www.amd.comFlash MemoryProduct InformationMirrorBitFlash InformationTechnical Documentation. The following is a partial list of documents closely related to this product: MirrorBitTM Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs
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TABLE OF CONTENTS
Continuity of Specifications . . . . . . . . . . . 3 Continuity of Ordering Part Numbers . . . . . 3 For More Information . . . . . . . . . . . . . . . . 3 Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . DQ2: Toggle Bit II . . . . . . . . . Reading Toggle Bits DQ6/DQ2 DQ5: Exceeded Timing Limits . DQ3: Sector Erase Timer . . . . DQ1: Write-to-Buffer Abort . . .
Toggle Bit Algorithm . . . . . . . . . . . . . . . . . . 34
General Description . . . . . . . . . . . . . . . . . . . . . . 2
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . 2 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .5 Special Package Handling Instructions . . . . 5 Look Ahead pinout . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10 Requirements for Reading Array Data . . . 10 Writing Commands/Command Sequences 11 Standby Mode ........................................................................ 11 Automatic Sleep Mode . . . . . . . . . . . . . . 11 RESET#: Hardware Reset Pin . . . . . . . . . 12 Output Disable Mode . . . . . . . . . . . . . . . 12
Device Bus Operations . . . . . . . . . . . . . . . . . 10
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34 35 35 35 35
37 37
Write Operation Status . . . . . . . . . . . . . . . . 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 37
Maximum Negative Overshoot Waveform . . Maximum Positive Overshoot Waveform . . .
Flash DC Characteristics . . . . . . . . . . . . . . . . . . . . 38 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . 39 Test Specifications . . . . . . . . . . . . . . . . . . . 39
Key to Switching Waveforms. . . . . . . . . . . . . . . . 39
Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 40 VCC Power-up ........................................................................ 40
VCC Power-up Diagram . . . . . . . . . . . . . . . . 40 Read Operations Timings . . . . . . . . . . . . . . . 41 Page Read Timings . . . . . . . . . . . . . . . . . . . 42
Hardware Reset (RESET#) .................................................... 43
Reset Timings . . . . . . . . . . . . . . . . . . . . . . Program Operation Timings . . . . . . . . . . Accelerated Program Timing Diagram. . . . Chip/Sector Erase Operation Timings . . . Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . Toggle Bit Timings (During Embedded Algorithms). . . . . . . . . . . . . . . . . . . . . . DQ2 vs. DQ6 . . . . . . . . . . . . . . . . . . . . . 43
SecSi (Secured Silicon) Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . 17
SecSi Sector Contents . . . . . . . . . . . . . . . . 18
Sector Address Table . . . . . . . . . . . . . . . . . . 12
Erase and Program Operations .............................................. 44
. . . 45 . . 45 . . . 46 . . . 47 . . 48 . . . 48
Sector Group Protection and Unprotection............................. 19
Sector Group Protection/Unprotection Address Table . . . . . . . . . . . . . . . . . . . . . . 19
Write Protect (WP#) ................................................................ 20 Temporary Sector Group Unprotect . . . . . 20
Temporary Sector Group Unprotect Operation 20 In-System Sector Group Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 21
Temporary Sector Unprotect .................................................. 49
Temporary Sector Group Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . 49 Sector Group Protect and Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . 50
Hardware Data Protection . . . . . . . . . . . 22 Common Flash Memory Interface (CFI) . . . . . . . . 22 Command Definitions . . . . . . . . . . . . . . . . . . . . . . .24 Reading Array Data . . . . . . . . . . . . . . . . 24 Reset Command . . . . . . . . . . . . . . . . . . 25 Autoselect Command Sequence . . . . . . . 25 Enter SecSi Sector/Exit SecSi Sector Command Sequence . . . . . . . . . . . . . . . 25 Word Program Command Sequence . . . . . 25 Program Suspend/Program Resume Command Sequence . . . . . . . . . . . . . . . 29 Chip Erase Command Sequence . . . . . . . 30 Sector Erase Command Sequence . . . . . . 30
Write Buffer Programming Operation . . . . . . . 28 Program Operation . . . . . . . . . . . . . . . . . . . 29
Alternate CE# Controlled Erase and Program Operations .............................................................................. 51
Alternate CE# Controlled Write (Erase/Program) Operation Timings 5. . . . . . . . . . . . . . . . . . . . 2
Program Suspend/Program Resume . . . . . . . 30
Erase Suspend/Erase Resume Commands 31 Command Definitions .............................................................. 32 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 33 DQ7: Data# Polling . . . . . . . . . . . . . . . . 33 DQ6: Toggle Bit I. . . . . . . . . . . . . . . . . . 33
Erase Operation . . . . . . . . . . . . . . . . . . . . . 31
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 52 Erase And Programming Performance. . . . . . . . . 53 BGA Package Capacitance. . . . . . . . . . . . . . . . . . 53 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Function Truth Table . . . . . . . . . . . . . . . . . . . . . . . 55 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Recommended Operating Conditions . . . . . . . . . 57 pSRAM DC Characteristics . . . . . . . . . . . . . . . . . . 58 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . . 59 Read Operation . . . . . . . . . . . . . . . . . . . 59 Write Operation . . . . . . . . . . . . . . . . . . 60 Power Down Parameters . . . . . . . . . . . . 61 Other Timing Parameters . . . . . . . . . . . . 61 AC Test Conditions . . . . . . . . . . . . . . . . . 62
AC Measurement Output Load Circuit . . . . . . 62
Data# Polling Algorithm . . . . . . . . . . . . . . . . 33
Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 63
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Read TIming #1 (Basic Timing) . . . . . . . . . . 63 Read Timing #2 (OE# and Address Access) . . 64 Read Timing #3 (LB#/UB# Byte Access) . . . . 65 Read Timing #4 (Page Access after CE1# Control Access) . . . . . . . . . . . . . . . . . . . . . 65 Read Timing #5 (Random and Page Address Access) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Write Timing #1 (Basic Timing) . . . . . . . . . . 67 Write Timing #2 (WE# Control) . . . . . . . . . . 67 Write Timing #3-1 (WE#/LB#/UB# Byte Write Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Write Timing #3-2 (WE#/LB#/UB# Byte Write Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Write Timing #3-3 (WE#/LB#/UB# Byte Write Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Write Timing #3-4 (WE#/LB#/UB# Byte Write Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Read/Write Timing #1-1 (CE1# Control) . . . 71 Read/Write Timing #1-2 (CE1#/WE#/OE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Read/Write Timing #2 (OE#, WE# Control) . 72 Read/Write Timing #3 (OE#, WE#, LB#, UB# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Power-up Timing #1 . . . . . . . . . . . . . . . . . 73 Power-up Timing #2 . . . . . . . . . . . . . . . . . 73 Power-down Entry and Exit Timing. . . . . . . . 74 Standby Entry Timing after Read or Write . . . 74
AM49LV128BM MCP With Second PSRAM Supplier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 pSRAM Block Diagram . . . . . . . . . . . . . . . . . . . . . 76 Absolute Maximum Ratings (Note 1) . . . . . . . . . .76
Operating Characteristics (Over Specified Temperature Range) . . . . . . . . . . . . . . . . . . . . . . . 77 Output Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . 78 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Timing of Read Cycle (CE# = OE# = VIL, WE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Timing Waveform of Read Cycle (WE#=VIH) . . . 81 Timing Waveform of Page Mode Read Cycle (WE# = VIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Timing Waveform of Write Cycle (WE# Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timing Waveform of Write Cycle (CE# Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Timing Waveform for Successive WE# Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Timing Waveform of Page Mode Write Cycle. . 86 Reduced Memory Size (RMS) . . . . . . . . . 86 Partial Array Refresh (PAR) . . . . . . . . . . . 86 Deep Sleep Mode . . . . . . . . . . . . . . . . . . 87 Variable Address Register . . . . . . . . . . . . . . . . . . 88 Variable Address Register (VAR) Update Timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Deep Sleep Mode - Entry/Exit Timings . . . . . . . . 90 Address Patterns for PAR (A3 = 0, A4 = 1) . . . . . . 91 Address Patterns for RMS (A3 = 1, A4 = 1) . . . . . 92 Low Power ICC Characteristics for PSRAM . . . . 93 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 94 TLD064-64-Ball Fine-pitch Ball Grid Array ............................. 94 Revision Summary. . . . . . . . . . . . . . . . . . . . . . . . . 95
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PRODUCT SELECTOR GUIDE
Part Number Speed/ Voltage Option Max. Access Time (ns) Max. CE# Access Time (ns) Max. Page access time (tPACC) Max. OE# Access Time (ns)
Notes: 1. See "AC Characteristics" for full specifications.
Am49LV128BM Full Voltage Range VCC = 2.7-3.1 V Flash 15 105 105 25 25 11 110 110 30 30 pSRAM 15, 11 65 65 20 20
MCP BLOCK DIAGRAM
A22 to A0 A22 to A0 WP#/ACC RESET# CE#f RY/BY#
128 M Bit Flash Memory DQ15 to DQ0
DQ15 to DQ0 VCCs/VCCQ VSS/VSSQ
A0 toto A0 A20 A19 LB#ps UB#ps WE# OE# CE1#ps CE2ps 32 M Bit pseudo Static RAM
DQ15 to DQ0
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CONNECTION DIAGRAMS
64-Ball Fine-Pitch (FBGA) Top View, Balls Facing Down
A1 NC B5 NC C3 A7 D2 A3 E2 A2 F2 A1 G2 A0 H2 CE#f J2 CE#1ps D3 A6 E3 A5 F3 A4 G3 VSS H3 OE# J3 DQ0 K3 DQ8 C4 LB# D4 UB# E4 A18 F4 A17 G4 DQ1 H4 DQ9 J4 DQ10 K4 DQ2 H5 DQ3 J5 VCCf K5 DQ11 L5 NC M1 NC H6 DQ4 J6 VCCps K6 NC L6 NC C5 WP/ACC# D5 RESET# E5 RY/BY# B6 NC C6 WE# D6 CE2ps E6 A20 C7 A8 D7 A19 E7 A9 F7 A10 G7 DQ6 H7 DQ13 J7 DQ12 K7 DQ5 C8 A11 D8 A12 E8 A13 F8 A14 G8 NC H8 DQ15 J8 DQ7 K8 DQ14 D9 A15 E9 A21 F9 A22 G9 A16 H9 VCCf J9 VSS
A10 NC
M10 NC
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package
and/or data integrity may be compromised if the package body is exposed to temperatures above 150C for prolonged periods of time.
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LOOK AHEAD PINOUT
A1
NC
A2
NC
A9
NC
A10
NC
B1
NC
B2
NC
B9
NC
B10
NC
C2
ADV#
C3
VSSds
C4
CLK
C5 D5 E5
RST#f
C6 D6 E6
CE2s1
C7 D7
A8
C8 D8
A11
C9 D9
CE#1ds
CE#f2 VCCds RST#ds CLK#ds RY/BY#ds
D2
WP#
D3
A7
D4
LB#
Pseudo SRAM Only Flash Only
WP/ACC WE#
E2
A3
E3
A6
E4
UB#s
E7
A19
E8
A12
E9
A15
Shared
F2
A2
F3
A5
F4
A18
F5
RY/BY#
F6
A20
F7
A9
F8
A14
F9
A22
G2
A0
G3
VSS
G4
DQ1
G5
VCCf
G6
VCCps
G7
DQ6
G8
NC
G9
A16
H2
CE#f1
H3
OE#
H4
DQ9
H5
DQ3
H6
DQ4
H7
DQ13
H8
DQ15
H9
NC
J2
CE#1ps
J3
DQ0
J4
DQ10
J5
VCCf
J6
VCCps
J7
DQ12
J8
DQ7
J9
VSS
K2
CE#1ps
K3
DQ8
K4
DQ2
K5
DQ11
K6
NC
K7
DQ5
K8 L8 M8
K9 L9 M9 N9
NC
DQ14 CE#1ps
L2
CE#1ps
L3
DQ8
L4
DQ2
L5
DQ11
L6
NC
L7
DQ5
DQ14 CE#1ps
M2
CE#1ps
M3
DQ8
M4
DQ2
M5
DQ11
M6
NC
M7
DQ5
DQ14 CE#1ps
N1
NC
N2
NC
N10
NC
P1
NC
P2
NC
P9
NC
P10
NC
In order to provide customers with a migration path to higher densities, as well as the option to stack more die in a package, FASL has prepared a standard pinout that supports:
NOR Flash and SRAM densities up to 4 Gigabits NOR Flash and pSRAM densities up to 4 Gigabits NOR Flash and pSRAM and DATA STORAGE densities up to 4 Gigabits.
tual package outline may vary. However, any pinout in any MCP will be a subset of the pinout above. In some cases, there may be outrigger balls in locations outside the grid shown above. In such cases, the user is recommended to treat these as RFU's, and not connect them to any other signal. In case of any further inquiries about the above lookahead pinout, please refer to the application note on this subject, or contact the appropriate AMD or Fujitsu sales office.
The signal locations of the resultant MCP device are shown above. Note that for different densities, the ac-
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Am49LV128BM
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PIN DESCRIPTION
A22-A21 A20-A0 = 2 Address inputs (Flash) = 21 Address inputs (Flash and pSRAM)
LOGIC SYMBOL
23 A22-21 A20-A0 CE1#ps CE2ps OE# WE# WP#/ACC RESET#f UB#s LB#s RY/BY# DQ15-DQ0 16
DQ14-DQ0 = 15 Data inputs/outputs DQ15 CE#f = DQ15 (Data input/output) = Chip Enable input (Flash)
CE1#ps, CE2ps=Chip Enable (pSRAM) OE# WE# WP#/ACC RESET#f VCCf = Output Enable input (Flash) = Write Enable input (Flash) = Hardware Write Protect input/Programming Acceleration input (Flash) = Hardware Reset Pin input (Flash) = Flash 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) = pSRAM Power Supply = Device Ground = Pin Not Connected Internally = Upper Byte Control (pSRAM) = Lower Byte Control (pSRAM) = Ready/Busy Output
VCCps VSS NC UB#s LB#s RY/BY#
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ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am49LV128 B M a H 10 N T
TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE N = Light Industrial (-25C to +85C) SPEED OPTION See Product Selector Guide and Valid Combinations WP# PROTECTION H = High sector protection L = Low sector protection pSRAM Blank= Standard Supplier a = Second Supplier PROCESS TECHNOLOGY M= 0.23 m MirrorBit pSRAM DEVICE DENSITY B = 32 Mbits AMD DEVICE NUMBER/DESCRIPTION Am49LV128BM Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM Am29LV128M 128 Megabit (8 M x 16-Bit) Flash Memory and 32 Mbit (2 M x 16-Bit) pseudo Static RAM
Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations
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Am49LV128BM
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DEVICE BUS OPERATIONS
This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The contents of the Table 1.
Operation Read Write (Program/Erase) Accelerated Program Standby Output Disable Reset Sector Group Protect (Note 2) Sector Group Unprotect (Note 2) Temporary Sector Group Unprotect CE# L L L VCC 0.3 V L X L OE# L H H X H X H WE# H L L X H X L
register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail.
Device Bus Operations
RESET# H H H VCC 0.3 V H L VID WP# ACC Addresses (Note 2) AIN AIN AIN X X X SA, A6 =L, A3=L, A2=L, A1=H, A0=L SA, A6=H, A3=L, A2=L, A1=H, A0=L AIN
DQ0- DQ7 DOUT (Note 4) (Note 4) High-Z High-Z High-Z (Note 4)
DQ8- DQ15 DOUT (Note 4) (Note 4) High-Z High-Z High-Z X
X (Note 3) (Note 3) X X X H
X X VHH H X X X
L
H
L
VID
H
X
(Note 4)
X
X
X
X
VID
H
X
(Note 4)
(Note 4)
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5-12.5 V, VHH = 11.5-12.5 V, X = Don't Care, SA = Sector Address, AIN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. Addresses are A22:A0. Sector addresses are A22:A15 in both modes. 2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the "Sector Group Protection and Unprotection" section. 3. If WP# = VIL, the first or last sector remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as determined by the method described in "Write Protect (WP#)". All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version ordered.) 4. DIN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See "Reading Array Data" for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data.
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Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read operation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words. The appropriate page is selected by the higher address bits A(max)-A2. Address bits A1-A0 determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to tACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to tPACC. When CE# is deasserted and reasserted for a subsequent access, the access time is tACC or tCE. Fast page mode accesses are obtained by keeping the "read-page addresses" constant and changing the "intra-read page" addresses.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Autoselect Functions If the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7-DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The "Word Program Command Sequence" section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system write to a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See "Write Buffer" for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput at the factory.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VIO 0.3 V. (Note that this is a more restricted voltage range than V IH .) If CE# and RESET# are held at V IH , but not within V IO 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification.
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RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS0.3 V, the device draws CMOS standby current (I CC4 ). If RESET# is held at VIL but not within VSS0.3 V, the standby current will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. Refer to the AC Characteristics tables for RESET# parameters and to Figure 16 for the timing diagram. VCC Power-up and Power-down Sequencing The device imposes no restrictions on VCC power-up or power-down sequencing. Asserting RESET# to VIL is required during the entire VCC power sequence until the respective supplies reach their operating voltages. Once VCC attains its operating voltage, de-assertion of RESET# to VIH is permitted.
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
Table 2.
Sector Address Table
Sector Size (Kwords) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 000000-007FFF 008000-00FFFF 010000-017FFF 018000-01FFFF 020000-027FFF 028000-02FFFF 030000-037FFF 038000-03FFFF 040000-047FFF 048000-04FFFF 050000-057FFF 058000-05FFFF 060000-067FFF 068000-06FFFF 070000-077FFF 078000-07FFFF 080000-087FFF 088000-08FFFF 090000-097FFF 098000-09FFFF 0A0000-0A7FFF 0A8000-0AFFFF 0B0000-0B7FFF 0B8000-0BFFFF 0C0000-0C7FFF 0C8000-0CFFFF 0D0000-0D7FFF 0D8000-0DFFFF 0E0000-0E7FFF
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A22-A15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
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Table 2.
Sector Address Table (Continued)
Sector Size (Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 0E8000-0EFFFF 0F0000-0F7FFF 0F8000-0FFFFF 100000-107FFF 108000-10FFFF 110000-117FFF 118000-11FFFF 120000-127FFF 128000-12FFFF 130000-137FFF 138000-13FFFF 140000-147FFF 148000-14FFFF 150000-157FFF 158000-15FFFF 160000-167FFF 168000-16FFFF 170000-177FFF 178000-17FFFF 180000-187FFF 188000-18FFFF 190000-197FFF 198000-19FFFF 1A0000-1A7FFF 1A8000-1AFFFF 1B0000-1B7FFF 1B8000-1BFFFF 1C0000-1C7FFF 1C8000-1CFFFF 1D0000-1D7FFF 1D8000-1DFFFF 1E0000-1E7FFF 1E8000-1EFFFF 1F0000-1F7FFF 1F8000-1FFFFF 200000-207FFF 208000-20FFFF 210000-217FFF 218000-21FFFF 220000-227FFF 228000-22FFFF 230000-237FFF 238000-23FFFF 240000-247FFF 248000-24FFFF 250000-257FFF 258000-25FFFF 260000-267FFF
Sector SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
A22-A15 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
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Table 2.
Sector Address Table (Continued)
Sector Size (Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 268000-26FFFF 270000-277FFF 278000-27FFFF 280000-287FFF 288000-28FFFF 290000-297FFF 298000-29FFFF 2A0000-2A7FFF 2A8000-2AFFFF 2B0000-2B7FFF 2B8000-2BFFFF 2C0000-2C7FFF 2C8000-2CFFFF 2D0000-2D7FFF 2D8000-2DFFFF 2E0000-2E7FFF 2E8000-2EFFFF 2F0000-2F7FFF 2F8000-2FFFFF 300000-307FFF 308000-30FFFF 310000-317FFF 318000-31FFFF 320000-327FFF 328000-32FFFF 330000-337FFF 338000-33FFFF 340000-347FFF 348000-34FFFF 350000-357FFF 358000-35FFFF 360000-367FFF 368000-36FFFF 370000-377FFF 378000-37FFFF 380000-387FFF 388000-38FFFF 390000-397FFF 398000-39FFFF 3A0000-3A7FFF 3A8000-3AFFFF 3B0000-3B7FFF 3B8000-3BFFFF 3C0000-3C7FFF 3C8000-3CFFFF 3D0000-3D7FFF 3D8000-3DFFFF 3E0000-3E7FFF
Sector SA77 SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A22-A15 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
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Table 2.
Sector Address Table (Continued)
Sector Size (Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 3E8000-3EFFFF 3F0000-3F7FFF 3F8000-3FFFFF 400000-407FFF 408000-40FFFF 410000-417FFF 418000-41FFFF 420000-427FFF 428000-42FFFF 430000-437FFF 438000-43FFFF 440000-447FFF 448000-44FFFF 450000-457FFF 458000-45FFFF 460000-467FFF 468000-46FFFF 470000-477FFF 478000-47FFFF 480000-487FFF 488000-48FFFF 490000-497FFF 498000-49FFFF 4A0000-4A7FFF 4A8000-4AFFFF 4B0000-4B7FFF 4B8000-4BFFFF 4C0000-4C7FFF 4C8000-4CFFFF 4D0000-4D7FFF 4D8000-4DFFFF 4E0000-4E7FFF 4E8000-4EFFFF 4F0000-4F7FFF 4F8000-4FFFFF 500000-507FFF 508000-50FFFF 510000-517FFF 518000-51FFFF 520000-527FFF 528000-52FFFF 530000-537FFF 538000-53FFFF 540000-547FFF 548000-54FFFF 550000-557FFF 558000-55FFFF 560000-567FFF
Sector SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
A22-A15 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
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Table 2.
Sector Address Table (Continued)
Sector Size (Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 568000-56FFFF 570000-577FFF 578000-57FFFF 580000-587FFF 588000-58FFFF 590000-597FFF 598000-59FFFF 5A0000-5A7FFF 5A8000-5AFFFF 5B0000-5B7FFF 5B8000-5BFFFF 5C0000-5C7FFF 5C8000-5CFFFF 5D0000-5D7FFF 5D8000-5DFFFF 5E0000-5E7FFF 5E8000-5EFFFF 5F0000-5F7FFF 5F8000-5FFFFF 600000-607FFF 608000-60FFFF 610000-617FFF 618000-61FFFF 620000-627FFF 628000-62FFFF 630000-637FFF 638000-63FFFF 640000-647FFF 648000-64FFFF 650000-657FFF 658000-65FFFF 660000-667FFF 668000-66FFFF 670000-677FFF 678000-67FFFF 680000-687FFF 688000-68FFFF 690000-697FFF 698000-69FFFF 6A0000-6A7FFF 6A8000-6AFFFF 6B0000-6B7FFF 6B8000-6BFFFF 6C0000-6C7FFF 6C8000-6CFFFF 6D0000-6D7FFF 6D8000-6DFFFF 6E0000-6E7FFF
Sector SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A22-A15 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1
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Table 2.
Sector Address Table (Continued)
Sector Size (Kwords) 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16-bit Address Range (in hexadecimal) 6E8000-6EFFFF 6F0000-6F7FFF 6F8000-6FFFFF 700000-707FFF 708000-70FFFF 710000-717FFF 718000-71FFFF 720000-727FFF 728000-72FFFF 730000-737FFF 738000-73FFFF 740000-747FFF 748000-74FFFF 750000-757FFF 758000-75FFFF 760000-767FFF 768000-76FFFF 770000-777FFF 778000-77FFFF 780000-787FFF 788000-78FFFF 790000-797FFF 798000-79FFFF 7A0000-7A7FFF 7A8000-7AFFFF 7B0000-7B7FFF 7B8000-7BFFFF 7C0000-7C7FFF 7C8000-7CFFFF 7D0000-7D7FFF 7D8000-7DFFFF 7E0000-7E7FFF 7E8000-7EFFFF 7F0000-7F7FFF 7F8000-7FFFFF
Sector SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230 SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A22-A15 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
SecSi (Secured Silicon) Sector Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either customer lockable (standard shipping option) or factory locked (contact an AMD sales representative for ordering information). The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to program the sector after receiving the device. The customer-lockable version also has the SecSi Sector Indicator Bit permanently set to a "0." The factory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a "1." Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. Note that the ACC 17
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function and unlock bypass modes are not available when the SecSi Sector is enabled. The SecSi sector address space in this device is allocated as follows: Table 3.
SecSi Sector Address Range 000000h-000007h 000008h-00007Fh
area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. An ESN Factory Locked device has an 16-byte random ESN at addresses 000000h-000007h. Please contact your local AMD sales representative for details on ordering ESN Factory Locked devices. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service (Express Flash Factory Locked). The devices are then shipped from AMD's factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD's ExpressFlash service. Note: MCP devices with second supplier pSRAM have 000000h address programmed to 0000h data.
SecSi Sector Contents
Customer Lockable ESN Factory Locked ESN Unavailable ExpressFlash Factory Locked ESN or determined by customer Determined by customer
Determined by customer
The system accesses the SecSi Sector through a command sequence (see "Enter SecSi Sector/Exit SecSi Sector Command Sequence"). After the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the addresses normally occupied by the first sector (SA0). This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory Unless otherwise specified, the device is shipped such that the customer may program and protect the 256byte SecSi sector. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming command sequence. See Command Definitions. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector
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Sector Group Protection and Unprotection
The hardware sector group protection feature disables both program and erase operations in any sector group. The hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. Sector group protection/unprotection can be implemented via two methods. Sector group protection/unprotection requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment. Figure 2 shows the algorithms and Figure 24 shows the timing diagram. This method uses standard microprocessor bus cycle timing. For sector group unprotect, all unprotected sector group must first be protected prior to the first sector group unprotect write cycle. The device is shipped with all sector groups unprotected. AMD offers the option of programming and protecting sector groups at its factory prior to shipping the device through AMD's ExpressFlashTM Service. Contact an AMD representative for details. It is possible to determine whether a sector group is protected or unprotected. See the Sector Group Protection and Unprotection section for details. Table 4. Sector Group Protection/Unprotection Address Table
A22-A15 00000000 00000001 00000010 00000011 000001xx 000010xx 000011xx 000100xx 000101xx 000110xx 000111xx 001000xx 001001xx 001010xx 001011xx 001100xx 001101xx 001110xx 001111xx 010000xx 010001xx 010010xx 010011xx SA0 SA1 SA2 SA3 SA4-SA7 SA8-SA11 SA12-SA15 SA16-SA19 SA20-SA23 SA24-SA27 SA28-SA31 SA32-SA35 SA36-SA39 SA40-SA43 SA44-SA47 SA48-SA51 SA52-SA55 SA56-SA59 SA60-SA63 SA64-SA67 SA68-SA71 SA72-SA75 SA76-SA79
Sector Group SA80-SA83 SA84-SA87 SA88-SA91 SA92-SA95 SA96-SA99 SA100-SA103 SA104-SA107 SA108-SA111 SA112-SA115 SA116-SA119 SA120-SA123 SA124-SA127 SA128-SA131 SA132-SA135 SA136-SA139 SA140-SA143 SA144-SA147 SA148-SA151 SA152-SA155 SA156-SA159 SA160-SA163 SA164-SA167 SA168-SA171 SA172-SA175 SA176-SA179 SA180-SA183 SA184-SA187 SA188-SA191 SA192-SA195 SA196-SA199 SA200-SA203 SA204-SA207 SA208-SA211 SA212-SA215 SA216-SA219 SA220-SA223 SA224-SA227 SA228-SA231 SA232-SA235 SA236-SA239 SA240-SA243 SA244-SA247 SA248-SA251 SA252 SA253 SA254 SA255
A22-A15 010100xx 010101xx 010110xx 010111xx 011000xx 011001xx 011010xx 011011xx 011100xx 011101xx 011110xx 011111xx 100000xx 100001xx 100010xx 100011xx 100100xx 100101xx 100110xx 100111xx 101000xx 101001xx 101010xx 101011xx 101100xx 101101xx 101110xx 101111xx 110000xx 110001xx 110010xx 110011xx 110100xx 110101xx 110110xx 110111xx 111000xx 111001xx 111010xx 111011xx 111100xx 111101xx 111110xx 11111100 11111101 11111110 11111111
Sector Group
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Write Protect (WP#)
The Write Protect function provides a hardware method of protecting the last sector without using VID. Write Protect is one of two functions provided by the WP#/ACC input. If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the last sector independently of whether those sectors were protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that if WP#/ACC is at V IL when the device is in the standby mode, the maximum input load current is increased. See the table in "DC Characteristics". If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the last sector was previously set to be protected or unprotected using the method described in "Sector Group Protection and Unprotection". Note that WP# has an internal pullup; when unconnected, WP# is at VIH.
START
RESET# = VID (Note 1) Perform Erase or Program Operations
RESET# = VIH
Temporary Sector Group Unprotect Completed (Note 2)
Temporary Sector Group Unprotect
This feature allows temporary unprotection of previously protected sector groups to change data in-system. The Sector Group Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once V ID is removed from the RESET# pin, all the previously protected sector groups are protected again. Figure 1 shows the algorithm, and Figure 23 shows the timing diagrams, for this feature.
Notes: 1. All protected sector groups unprotected (If WP# = VIL, the last sector group will remain protected). 2. All previously protected sector groups are protected once again.
Figure 1. Temporary Sector Group Unprotect Operation
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START PLSCNT = 1 RESET# = VID Wait 1 s Protect all sectors: The indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address
START PLSCNT = 1 RESET# = VID Wait 1 s
Temporary Sector Unprotect Mode
No
First Write Cycle = 60h? Yes Set up sector address Sector Protect: Write 60h to sector address with A6 = 0, A1 = 1, A0 = 0 Wait 150 s Verify Sector Protect: Write 40h to sector address with A6 = 0, A1 = 1, A0 = 0 Read from sector address with A6 = 0, A1 = 1, A0 = 0 No
No First Write Cycle = 60h? Yes All sectors protected? Yes Set up first sector address Sector Unprotect: Write 60h to sector address with A6 = 1, A1 = 1, A0 = 0
Temporary Sector Unprotect Mode
Increment PLSCNT
Reset PLSCNT = 1
Wait 15 ms Verify Sector Unprotect: Write 40h to sector address with A6 = 1, A1 = 1, A0 = 0
No No PLSCNT = 25? Yes Data = 01h?
Increment PLSCNT
Yes
No Yes No
Read from sector address with A6 = 1, A1 = 1, A0 = 0 Set up next sector address
Device failed
Protect another sector? No Remove VID from RESET#
PLSCNT = 1000? Yes
Data = 00h? Yes
Device failed Write reset command
Last sector verified? Yes
No
Sector Protect Algorithm
Sector Protect complete
Sector Unprotect Algorithm
Remove VID from RESET#
Write reset command Sector Unprotect complete
Figure 2.
In-System Sector Group Protect/Unprotect Algorithms
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Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 9 for command definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control
pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h, any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 5-8. To terminate reading CFI data, the system must write the reset command. Table 5.
Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah Data 0051h 0052h 0059h 0002h 0000h 0040h 0000h 0000h 0000h 0000h 0000h Query Unique ASCII string "QRY"
The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 5-8. The system must write the reset command to return the device to reading array data. For further information, please refer to the CFI Specification and CFI Publication 100, available via the World Wide Web at http://www.amd.com/flash/cfi. Alternatively, contact an AMD representative for copies of these documents.
CFI Query Identification String
Description
Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists)
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Table 6.
Addresses (x16) 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h Data 0027h 0036h 0000h 0000h 0007h 0007h 000Ah 0000h 0001h 0005h 0004h 0000h
System Interface String
Description
VCC Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VCC Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt VPP Min. voltage (00h = no VPP pin present) VPP Max. voltage (00h = no VPP pin present) Typical timeout per single byte/word write 2N s Typical timeout for Min. size buffer write 2N s (00h = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2N ms (00h = not supported) Max. timeout for byte/word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 7.
Addresses (x16) 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch Data 0018h 0002h 0000h 0005h 0000h 0001h 00FFh 0000h 0000h 0001h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h
Device Geometry Definition
Description
Device Size =
2N
byte
Flash Device Interface description (refer to CFI publication 100) Max. number of byte in multi-byte write = 2N (00h = not supported) Number of Erase Block Regions within device (01h = uniform device, 02h = boot device) Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100)
Erase Block Region 2 Information (refer to CFI publication 100)
Erase Block Region 3 Information (refer to CFI publication 100)
Erase Block Region 4 Information (refer to CFI publication 100)
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Table 8.
Addresses (x16) 40h 41h 42h 43h 44h 45h Data 0050h 0052h 0049h 0031h 0033h 0008h
Primary Vendor-Specific Extended Query
Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) 0 = Required, 1 = Not Required Process Technology (Bits 7-2) 0010b = 0.23 m MirrorBit Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Sector Protect 0 = Not Supported, X = Number of sectors in per group Sector Temporary Unprotect 00 = Not Supported, 01 = Supported Sector Protect/Unprotect scheme 04 = 29LV800 mode Simultaneous Operation 00 = Not Supported, X = Number of Sectors in Bank Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page ACC (Acceleration) Supply Minimum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV Top/Bottom Boot Sector Flag 00h = Uniform Device without WP# protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Uniform sectors bottom WP# protect, 05h = Uniform sectors top WP# protect Program Suspend 00h = Not Supported, 01h = Supported
46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh
0002h 0001h 0001h 0004h 0000h 0000h 0001h 00B5h 00C5h
4Fh
0004h/ 0005h
50h
0001h
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-eraseJune 17, 2004
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Am49LV128BM
suspended sector. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram.
and determine whether or not a sector is protected. Tables 9 show the address and data requirements. The autoselect command sequence may be written to an address that is either in the read or erase-suspendread mode. The autoselect command may not be written while the device is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: A read cycle at address XX00h returns the manufacturer code. Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. A read cycle to an address containing a sector address (SA), and the address 02h on A7-A0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in Erase Suspend).
Reset Command
Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don't cares for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the device entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Programming operation, the system must write the Writeto-Buffer-Abort Reset command sequence to reset the device for the next operation.
Enter SecSi Sector/Exit SecSi Sector Command Sequence
The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 9 show the address and data requirements for both command sequences. See also "SecSi (Secured Silicon) Sector Flash Memory Region" for further information. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 9 show the address and data requirements for the word program command sequence.
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and device codes,
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When the Embedded Program algorithm is complete, the device then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Unlock Bypass Command Sequence The unlock bypass feature allows the system to program words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total programming time. Tables 9 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a
third write cycle containing the Write Buffer Load command written at the Sector Address in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will program 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is selected by address bits AMAX-A4. All subsequent address/data pairs must fall within the selected-writebuffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be performed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be performed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a writebuffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Program Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be suspended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways:
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Load a value that is greater than the page buffer size during the Number of Locations to Program step. Write to an address in a sector different than the one specified during the Write-Buffer-Load command. Write an Address/Data pair to a different writebuffer-page than the one selected by the Starting Address during the write buffer data loading stage of the operation. Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from "0" back to a "1." Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still "0." Only erase operations can convert a "0" to a "1." Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at VIH. Figure 5 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.
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Write "Write to Buffer" command and Sector Address
Write number of addresses to program minus 1(WC) and Sector Address
Part of "Write to Buffer" Command Sequence
Write first address/data
Yes
WC = 0 ? No Abort Write to Buffer Operation? No Yes Write to buffer ABORTED. Must write "Write-to-buffer Abort Reset" command sequence to return to read mode. Write to a different sector address
(Note 1)
Write next address/data pair
WC = WC - 1
Write program buffer to flash sector address
Notes:
1. When Sector Address is specified, any address in the selected sector is acceptable. However, when loading Write-Buffer address locations with data, all addresses must fall within the selected Write-Buffer Page.
Read DQ7 - DQ0 at Last Loaded Address
2. 3.
DQ7 may change simultaneously with DQ5. Therefore, DQ7 should be verified. If this flowchart location was reached because DQ5= "1", then the device FAILED. If this flowchart location was reached because DQ1= "1", then the Write to Buffer operation was ABORTED. In either case, the proper reset command must be written before the device can begin another operation. If DQ1=1, write the Write-Buffer-Programming-Abort-Reset command. if DQ5=1, write the Reset command.
See Tables 9 and 10 for command sequences required for write buffer programming.
DQ7 = Data? No No DQ1 = 1? Yes DQ5 = 1? Yes Read DQ7 - DQ0 with address = Last Loaded Address No
Yes
4.
(Note 2)
DQ7 = Data? No
Yes
(Note 3)
FAIL or ABORT
PASS
Figure 3. 28
Write Buffer Programming Operation Am49LV128BM June 17, 2004
time Program area), then the user must use the proper command sequences to enter and exit this region.
START
Write Program Command Sequence
The system may also write the autoselect command sequence when the device is in the Program Suspend mode. The system can read as many autoselect codes as required. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence for more information. After the Program Resume command is written, the device reverts to programming. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See Write Operation Status for more information.
No
Embedded Program algorithm in progress
Data Poll from System
Verify Data?
Yes No
Increment Address
Last Address?
The system must write the Program Resume command (address bits are don't care) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resume programming. There is no time-out limit for the Program Suspend command. After the Program Suspend command is written, the device will stay in Program Suspend mode until the Program Resume command or the RESET command/operation is written.
Yes Programming Completed
Note: See Tables 9 and 10 for program command sequence.
Figure 4.
Program Operation
Program Operation or Write-to-Buffer Sequence in Progress
Program Suspend/Program Resume Command Sequence
The Program Suspend command allows the system to interrupt a programming operation or a Write to Buffer programming operation so that data can be read from any non-suspended sector. Within the suspended sector, data may be read from addresses outside of the page (for example, Amax-A4) being programmed. When the Program Suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. Addresses are not required when writing the Program Suspend command. After the programming operation has been suspended, the system can read array data from any nonsuspended sector or from selected addresses within the suspended sector (see previous paragraph). The Program Suspend command may also be issued during a programming operation while an erase is suspended. In this case, data may be read from any sectors not in Erase Suspend or Program Suspend. If a read is needed from the SecSi Sector area (One-
Write address/data XXXh/B0h
Write Program Suspend Command Sequence Command is also valid for Erase-suspended-program operations
Wait 15 s
Read data as required
Autoselect and SecSi Sector read operations are also allowed Data cannot be read from erase- or program-suspended sectors
No
Done reading? Yes Write address/data XXXh/30h Write Program Resume Command Sequence
Device reverts to operation prior to Program Suspend
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Figure 5.
Program Suspend/Program Resume
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. Table 9 show the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 s occurs. During the time-out period, additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 s, otherwise erasure may begin. Any sector erase address and command following the exceeded timeout may or may not be accepted. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when an erase operation is in progress. The system must rewrite the command sequence and any additional addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, or DQ2 in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 6 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. Table 10 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto-
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START
Write Erase Command Sequence (Notes 1, 2)
When the Erase Suspend command is written during the sector erase operation, the device requires a typical of 5 s (maximum of 20 s) to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The system can read data from or program data to any sector not selected for erasure. (The device "erase suspends" all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status information on DQ7-DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. The address of the erase-suspended sector is required when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. There is no time-out limit for the Erase Suspend command. After the Erase Suspend command is written, the device will stay in Erase Suspend mode until the Erase Resume command or the RESET command/operation is written.
Data Poll to Erasing Bank from System
Embedded Erase algorithm in progress
No
Data = FFh?
Yes Erasure Completed
Figure 6.
Erase Operation
Notes: 1. See Tables 9 for erase command sequence. 2. See the section on DQ3 for information on the sector erase timer.
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm.
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31
Command Definitions
Table 9.
Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Autoselect (Note 8) Manufacturer ID Device ID (Note 9) SecSiTM Sector Factory Protect (Note 10) Sector Group Protect Verify (Note 12) Cycles First Addr RA XXX 555 555 555 555 555 555 555 555 SA 555 555 XXX XXX 555 555 BA BA 55 Data RD F0 AA AA AA AA AA AA AA AA 29 AA AA A0 90 AA AA B0 30 98 SA = Sector Address of sector to be verified (in autoselect mode) or erased. Address bits A22-A15 uniquely select any sector. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. 2AA 2AA PA XXX 2AA 2AA 55 55 PD 00 55 55 555 555 80 80 555 555 AA AA 2AA 2AA 55 55 555 SA 10 30 555 555 F0 20 2AA 2AA 2AA 2AA 2AA 2AA 2AA 2AA 55 55 55 55 55 55 55 55 555 555 555 555 555 555 555 SA 90 90 90 90 88 90 A0 25 XXX PA SA 00 PD WC PA PD WBL PD X00 X01 X03 (SA)X02 0001 227E (Note 10) 00/01 X0E 2212 X0F 2200
Command Definitions
Bus Cycles (Notes 2-5) Second Third Addr Data Fourth Addr Data Fifth Addr Data Sixth Addr Data
Addr
Data
1 1 4 4 4 4 3 4 4 3 1 3 3 2 2 6 6 1 1 1
Enter SecSi Sector Region Exit SecSi Sector Region Program Write to Buffer (Note 11) Program Buffer to Flash Write to Buffer Abort Reset (Note 13) Unlock Bypass Unlock Bypass Program (Note 14) Unlock Bypass Reset (Note 15) Chip Erase Sector Erase Program/Erase Suspend (Note 16) Program/Erase Resume (Note 17) CFI Query (Note 18)
Legend: X = Don't care RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. PA = Program Address. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later. PD = Program Data for location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first. Notes: 1. See Table 1 for description of bus operations. 2. 3. 4. 5. 6. 7. All values are in hexadecimal. Except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD, and WC. Unless otherwise noted, address bits A22-A11 are don't cares. No unlock or command cycles required when device is in read mode. The Reset command is required to return to the read mode (or to the erase-suspend-read mode if previously in Erase Suspend) when the device is in the autoselect mode, or if DQ5 goes high while the device is providing status information. The fourth cycle of the autoselect command sequence is a read cycle. Data bits DQ15-DQ8 are don't care. See the Autoselect Command Sequence section for more information. The device ID must be read in three cycles.
lowest address sector, the data is 88H for factory locked and 08H for not factory locked. 11. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 21. 12. The data is 00h for an unprotected sector and 01h for a protected sector. 13. Command sequence resets device for next command after aborted write-to-buffer operation. 14. The Unlock Bypass command is required prior to the Unlock Bypass Program command. 15. The Unlock Bypass Reset command is required to return to the read mode when the device is in the unlock bypass mode. 16. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation. 17. The Erase Resume command is valid only during the Erase Suspend mode.
18. Command is valid when device is ready to read array data or when device is in autoselect mode.
8.
9.
10. If WP# protects the highest address sector, the data is 98H for factory locked and 18H for not factory locked. If WP# protects the
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WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 10 and the following subsections describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a program or erase operation is complete or in progress. in the AC Characteristics section shows the Data# Polling timing diagram.
START
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Program or Erase algorithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 s, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a "0" on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status information on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 s, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ0-DQ7 will appear on successive read cycles. Table 10 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20
Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No No
DQ5 = 1?
Yes Read DQ7-DQ0 Addr = VA
DQ7 = Data?
Yes
No FAIL PASS
Notes: 1. VA = Valid address for programming. During a sector erase operation, a valid address is any sector address within the sector being erased. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be rechecked even if DQ5 = "1" because DQ7 may change simultaneously with DQ5.
Figure 7.
Data# Polling Algorithm
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
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Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 s, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the "AC Characteristics" section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II. Figure 8. Toggle Bit Algorithm
START
Read DQ7-DQ0
Read DQ7-DQ0
Toggle Bit = Toggle? Yes
No
No
DQ5 = 1?
Yes
Read DQ7-DQ0 Twice
Toggle Bit = Toggle?
No
Yes Program/Erase Operation Not Complete, Write Reset Command Program/Erase Operation Complete
Note: The system should recheck the toggle bit even if DQ5 = "1" because the toggle bit may stop toggling as DQ5 changes to "1." See the subsections on DQ6 and DQ2 for more information.
DQ2: Toggle Bit II
The "Toggle Bit II" on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare outputs for DQ2 and DQ6. Figure 9 shows the toggle bit algorithm in flowchart form, and the section "DQ2: Toggle Bit II" explains the algorithm. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form.
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Reading Toggle Bits DQ6/DQ2
Refer to Figure 9 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 9).
device halts the operation, and when the timing limit has been exceeded, DQ5 produces a "1." In all these cases, the system must write the reset command (or the Unlock Bypass Reset command if in Unlock Bypass mode) to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a "0" to a "1." If the time between additional sector erase commands from the system can be assumed to be less than 50 s, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is "1," the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is "0," the device will accept additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 10 shows the status of DQ3 relative to the other status bits.
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program, erase, or writeto-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a "1," indicating that the program or erase cycle was not successfully completed. The device may output a "1" on DQ5 if the system tries to program a "1" to a location that was previously programmed to "0." Only an erase operation can change a "0" back to a "1." Under this condition, the
DQ1: Write-to-Buffer Abort
DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a "1". The system must issue the Write-to-Buffer-AbortReset command sequence to return the device to reading array data. See Write Buffer Programming section for more details.
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Table 10.
Status Embedded Program Algorithm Embedded Erase Algorithm Program-Suspended ProgramSector Suspend Non-Program Read Suspended Sector Erase-Suspended EraseSector Suspend Non-Erase Suspended Read Sector Erase-Suspend-Program (Embedded Program) Busy (Note 3) Abort (Note 4)
Write Operation Status
DQ7 (Note 2) DQ7# 0 DQ6 Toggle Toggle DQ5 (Note 1) 0 0 DQ3 N/A 1 DQ2 (Note 2) No toggle Toggle DQ1 0 N/A
Standard Mode Program Suspend Mode
Invalid (not allowed) Data 1 No toggle 0 Data DQ7# DQ7# DQ7# Toggle Toggle Toggle 0 0 0 N/A N/A N/A N/A N/A N/A N/A 0 1 N/A Toggle N/A
Erase Suspend Mode
Write-toBuffer
Notes: 1. DQ5 switches to `1' when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the maximum timing limits. Refer to the section on DQ5 for more information. 2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details. 3. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location. 4. DQ1 switches to `1' when the device has aborted the write-to-buffer operation.
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . -65C to +125C Voltage with Respect to Ground VCC (Note 1) . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V VIO . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to +4.0 V A9, OE#, ACC, and RESET# (Note 2) . . . . . . . . . . . . . . . . . . . .-0.5 V to +12.5 V All other pins (Note 1) . . . . . . -0.5 V to VCC +0.5 V Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may overshoot V SS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 10. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 11. 2. Minimum DC input voltage on pins A9, OE#, ACC, and RESET# is -0.5 V. During voltage transitions, A9, OE#, ACC, and RESET# may overshoot V SS to -2.0 V for periods of up to 20 ns. See Figure 10. Maximum DC input voltage on pin A9, OE#, ACC, and RESET# is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. 3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. +0.8 V -0.5 V -2.0 V 20 ns 20 ns 20 ns
Figure 9. Maximum Negative Overshoot Waveform
20 ns VCC +2.0 V VCC +0.5 V 2.0 V 20 ns 20 ns
Figure 10. Maximum Positive Overshoot Waveform
OPERATING RANGES
Light Industrial (N) Devices Ambient Temperature (TA) . . . . . . . . . -25C to +85C Supply Voltages VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7-3.1 V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
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FLASH DC CHARACTERISTICS CMOS Compatible
Parameter Symbol ILI ILIT ILR ILO ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VHH VID VOL VOH1 VOH2 VLKO Parameter Description (Notes) Input Load Current (1) ACC Input Load Current Reset Leakage Current Output Leakage Current VCC Active Read Current (2, 3) Test Conditions VIN = VSS to VCC, VCC = VCC max VCC = VCC max VCC = VCC max; RESET# = 12.5 V VOUT = VSS to VCC, VCC = VCC max CE# = VIL, OE# = VIH 5 MHz 1 MHz 15 15 30 10 50 1 1 1 -0.5 1.9 VCC = 2.7-3.1 V VCC = 2.7-3.1 V IOL = 4.0 mA, VCC = VCC min = VIO IOH = -2.0 mA, VCC = VCC min = VIO IOH = -100 A, VCC = VCC min = VIO 0.85 VIO VIO-0.4 2.3 2.5 11.5 11.5 Min Typ Max 1.0 35 35 1.0 20 20 50 20 60 5 5 5 0.8 VCC + 0.5 12.5 12.5 0.15 x VIO Uni t A A A A mA mA mA mA A A A V V V V V V V V
VCC Initial Page Read Current (2, 3) CE# = VIL, OE# = VIH VCC Intra-Page Read Current (2, 3) CE# = VIL, OE# = VIH VCC Active Write Current (3, 4) VCC Standby Current (3) VCC Reset Current (3) Automatic Sleep Mode (3, 5) Input Low Voltage 1(6, 7) Input High Voltage 1 (6, 7) Voltage for ACC Program Acceleration Voltage for Autoselect and Temporary Sector Unprotect Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage (7)
5. 6. 7. 8. 9.
CE# = VIL, OE# = VIH CE#, RESET# = VCC 0.3 V, WP# = VIH RESET# = VSS 0.3 V, WP# = VIH VIH = VCC 0.3 V; VIL = VSS 0.3 V, WP# = VIH
Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is 5.0 A. 2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. 4. Maximum ICC specifications are tested with VCC = VCCmax. ICC active while Embedded Erase or Embedded Program is in progress.
Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. If VIO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. Maximum VIH for these connections is VIO + 0.3 V VCC voltage requirements. VIO voltage requirements. Not 100% tested.
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TEST CONDITIONS
Table 11.
3.3 V 2.7 k Test Condition Output Load Output Load Capacitance, CL (including jig capacitance) CL 6.2 k Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels (See Note) Note: Diodes are IN3064 or equivalent Output timing measurement reference levels
Test Specifications
All Speeds 1 TTL gate 30 5 0.0-3.0 1.5 0.5 VIO pF ns V V V Unit
Device Under Test
Figure 11.
Test Setup
Note: If VIO < VCC, the reference level is 0.5 VIO.
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS Steady Changing from H to L Changing from L to H Don't Care, Any Change Permitted Does Not Apply Changing, State Unknown Center Line is High Impedance State (High Z) OUTPUTS
3.0 V 0.0 V
Input
1.5 V
Measurement Level
0.5 VIO V
Output
Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.
Figure 12. Input Waveforms and Measurement Levels
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AC CHARACTERISTICS VCC Power-up
Parameter tVCS tRSTH
Description VCC Setup Time RESET# Low Hold Time
Test Setup Min Min
Speed 50 50
Unit s s
tVCS
VCC
tRSTH
RESET#
Figure 13.
VCC Power-up Diagram
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AC CHARACTERISTICS Flash Read-Only Operations
Parameter JEDEC tAVAV tAVQV tELQV Std. tRC tACC tCE Description Read Cycle Time (Note 1) Address to Output Delay Chip Enable to Output Delay CE#, OE# = VIL OE# = VIL Test Setup Min Max Max Max Max Max Max Min Min Min 15 105 105 105 25 25 14 14 0 0 10 11 110 110 110 30 30 Unit ns ns ns ns ns ns ns ns ns ns
tPACC Page Access Time tGLQV tEHQZ tGHQZ tAXQX tOE tDF tDF tOH Output Enable to Output Delay Chip Enable to Output Bus Release (Note 1) Output Enable to Output Bus Release (Note 1) Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First
Read Output Enable Hold tOEH Toggle and Time (Note 1) Data# Polling
Notes: 1. Not 100% tested. 2. See Figure 12 and Table 11 for test specifications. 3. AC Specifications are tested with VIO = VCC. Contact AMD for information on AC operations with VIO VCC.
tRC Addresses CE# tOE tOEH WE# HIGH Z Outputs RESET# RY/BY# Output Valid tCE tOH HIGH Z tDF Addresses Stable tACC
OE#
0V
Figure 14.
Read Operations Timings
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41
AC CHARACTERISTICS
A22-A2 Same Page
A1-A0
Aa
tACC
Ab
tPACC
Ac
tPACC tPACC
Ad
Data Bus CE# OE#
Figure 15.
Qa
Qb
Qc
Qd
Page Read Timings
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AC CHARACTERISTICS Hardware Reset (RESET#)
Parameter JEDEC Std. tReady tReady tRP tRH tRPD Description RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) RESET# Pulse Width Reset High Time Before Read (See Note) RESET# Low to Standby Mode Max Max Min Min Min 20 500 500 50 20 Unit s ns ns ns s
Note: Not 100% tested.
CE#, OE# tRH RESET# tRP tReady
Reset Timings NOT during Embedded Algorithms Reset Timings during Embedded Algorithms
CE#, OE#
RESET# tRP
Figure 16.
Reset Timings
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AC CHARACTERISTICS Erase and Program Operations
Parameter JEDEC tAVAV tAVWL Std. tWC tAS tASO tWLAX tAH tAHT tDVWH tWHDX tDS tDH tOEPH tGHWL tELWL tWHEH tWLWH tWHDL tGHWL tCS tCH tWP tWPH Description Write Cycle Time (Note 1) Address Setup Time Address Setup Time to OE# low during toggle bit polling Address Hold Time Address Hold Time From CE# or OE# high during toggle bit polling Data Setup Time Data Hold Time Output Enable High during toggle bit polling Read Recovery Time Before Write (OE# High to WE# Low) CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) tVHH tVCS VHH Rise and Fall Time (Note 1) VCC Setup Time (Note 1) Per Word Per Word Word Word Min Min Min Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ Min Min 15 105 0 15 45 0 45 0 20 0 0 0 35 30 240 15 11.8 60 54 0.5 250 50
11
110
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s sec ns s
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 words. 4. Effective write buffer specification is based upon a 16-word write buffer operation.
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AC CHARACTERISTICS
Program Command Sequence (last two cycles) tWC Addresses 555h tAS PA tAH CE# OE# tWP WE# tCS tDS Data tDH PD Status DOUT tWPH tWHWH1 PA PA Read Status Data (last two cycles)
tCH
A0h
VCC tVCS
Notes: 1. PA = program address, PD = program data, DOUT is the true data at the program address. 2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
VHH
ACC
VIL or VIH tVHH tVHH
VIL or VIH
Figure 18.
Accelerated Program Timing Diagram
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45
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) tWC Addresses 2AAh tAS SA
555h for chip erase
Read Status Data
VA tAH
VA
CE#
OE# tWP WE# tCS tDS
tCH
tWPH
tWHWH2
tDH Data tVCS VCC 55h 30h
10 for Chip Erase In Progress Complete
Notes: 1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see "Write Operation Status". 2. These waveforms are for the word mode.
Figure 19.
Chip/Sector Erase Operation Timings
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AC CHARACTERISTICS
tRC Addresses VA tACC tCE CE# tCH OE# tOEH WE# tOH DQ7
High Z
VA
VA
tOE tDF
Complement
Complement
True
Valid Data
High Z
DQ0-DQ6
Status Data
Status Data
True
Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 20.
Data# Polling Timings (During Embedded Algorithms)
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47
AC CHARACTERISTICS
tAHT Addresses
tAS
tAHT tASO CE# tOEH WE# tOEPH OE# tDH DQ6/DQ2 Valid Data
Valid Status
tCEPH
tOE
Valid Status Valid Status
Valid Data
(first read)
(second read)
(stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle
Figure 21.
Toggle Bit Timings (During Embedded Algorithms)
Enter Embedded Erasing WE#
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2 Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle DQ2 and DQ6.
Figure 22.
DQ2 vs. DQ6
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AC CHARACTERISTICS Temporary Sector Unprotect
Parameter JEDEC Std tVIDR tRSP Description VID Rise and Fall Time (See Note) RESET# Setup Time for Temporary Sector Unprotect Min Min 500 4 Unit ns s
Note: Not 100% tested.
VID RESET# VSS, VIL, or VIH tVIDR Program or Erase Command Sequence CE# tVIDR
VID VSS, VIL, or VIH
WE# tRSP
Figure 23.
Temporary Sector Group Unprotect Timing Diagram
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AC CHARACTERISTICS
VID VIH
RESET#
SA, A6, A1, A0
Valid* Sector Group Protect or Unprotect
Valid* Verify 40h
Sector Group Protect: 150 s, Sector Group Unprotect: 15 ms
Valid*
Data
60h
60h
Status
1 s CE#
WE#
OE#
* For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 24.
Sector Group Protect and Unprotect Timing Diagram
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AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations
Parameter JEDEC tAVAV tAVWL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std. tWC tAS tAH tDS tDH tGHEL tWS tWH tCP tCPH Description Write Cycle Time (Note 1) Address Setup Time Address Hold Time Data Setup Time Data Hold Time Read Recovery Time Before Write (OE# High to WE# Low) WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Write Buffer Program Operation (Notes 2, 3) Effective Write Buffer Program Operation (Notes 2, 4) tWHWH1 tWHWH1 Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Program Operation (Note 2) Accelerated Programming Operation (Note 2) tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Per Word Per Word Word Word Min Min Min Min Min Min Min Min Min Min Typ Typ Typ Typ Typ Typ 15, 11 65 0 45 45 0 0 0 0 45 30 240 15 11.8 60 54 0.5 Unit ns ns ns ns ns ns ns ns ns ns s s s s s sec
Notes: 1. Not 100% tested. 2. See the "Erase And Programming Performance" section for more information. 3. For 1-16 words. 4. Effective write buffer specification is based upon a 16-word write buffer operation.
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AC CHARACTERISTICS
555 for program 2AA for erase PA for program SA for sector erase 555 for chip erase
Data# Polling PA
Addresses tWC tWH WE# tGHEL OE# tCP CE# tWS tCPH tDS tDH Data tRH
A0 for program 55 for erase PD for program 30 for sector erase 10 for chip erase
tAS tAH
tWHWH1 or 2
tBUSY
DQ7#
DOUT
RESET#
Notes: 1. Figure indicates last two bus cycles of a program or erase operation. 2. PA = program address, SA = sector address, PD = program data. 3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device. 4. Waveforms are for the word mode.
Figure 25.
Alternate CE# Controlled Write (Erase/Program) Operation Timings
LATCHUP CHARACTERISTICS
Description Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Min -1.0 V -1.0 V -100 mA Max 12.5 V VCC + 1.0 V +100 mA
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
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ERASE AND PROGRAMMING PERFORMANCE
Parameter Sector Erase Time Chip Erase Time Effective Write Buffer Program Time (Note 3) Program Time Effective Accelerated Program Time (Note 3) Accelerated Program Time Chip Program Time (Note 4) Per Word Word Word Word Typ (Note 1) 0.5 128 15 60 11.8 54 126 1000 1000 785 900 Max (Note 2) 15 Unit sec sec s s s s sec Excludes system level overhead (Note 6) Comments Excludes 00h programming prior to erasure (Note 5)
Notes: 1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-word write buffer operation. 4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 7. The device has a minimum erase and program cycle endurance of 100,000 cycles.
BGA PACKAGE CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 FBGA FBGA FBGA Typ 4.2 5.4 3.9 Max 5 6.5 4.7 Unit pF pF pF
Notes: 1. Sampled, not 100% tested. 2. Test conditions TA = 25C, f = 1.0 MHz.
DATA RETENTION
Parameter Description Minimum Pattern Data Retention Time Test Conditions 150C 125C Min 10 20 Unit Years Years
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AM49LV128BM MCP WITH STANDARD SUPPLIER PSRAM BLOCK DIAGRAM
VDD VSS
A20 to A0
ADDRESS LATCH & BUFFER
ROW DECODER
MEMORY CELL ARRAY 33,554,432 bit
DQ16 to DQ9 DQ8 to DQ1
INPUT / OUTPUT BUFFER
INPUT DATA LATCH & CONTROL
SENSE / SWITCH
OUTPUT DATA CONTROL
COLUMN / DECODER
ADDRESS LATCH & BUFFER
CE2
POWER CONTROL TIMING CONTROL
CE1 WE LB UB OE
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FUNCTION TRUTH TABLE
Mode Standby (Deselect) Output Disable (Note 1) Output Disable (No Read) Read (Upper Byte) Read (Lower Byte) Read (Word) No Write Write (Upper Byte) Write (Lower Byte) Write (Word) Power Down (Note 2) Note:
1. Should not be kept this logic condition longer than 1 s.
CE2 H
CE1# H
WE# X H
OE# X H
LB# X H H H L L H H
UB# X X H L H L H L H L X
A20-0 X (Note 3) Valid Valid Valid Valid Valid Valid Valid Valid X
H H L
L
L
H (Note 4)
L L
L
X
X
4.
X
DQ7-0 DQ15-8 High-Z High-Z High-Z High-Z High-Z High-Z High-Z Output Valid Output High-Z Valid Output Output Valid Valid Invalid Invalid Invalid Input Valid Input Invalid Valid Input Input Valid Valid High-Z High-Z
2.
Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Refer to Power down for details. Can be either VIL or VIH but must be valid for read or write.
OE# can be VIL during Write operation if the following conditions are satisfied; Write pulse is initiated by CE1# (refer to CE1# Controlled Write timing), or cycle time of the previous operation cycle is satisfied, OE stays during Write cycle.
3.
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POWER DOWN
Power Down The Power Down is to enter low power idle state when CE2 stays Low. The pSRAM has two power down modes, Deep Sleep and 8M Partial. These can be programmed by series of read/write operation. See the following table for mode features.
Cycle# Operation 5th Write 6th Read Address 1FFFFFh Address Key Data X Read Data (RDb)
Mode Sleep (default) 8M Partial
Data Retention No 8M bit
Retention Address N/A 00000h to 7FFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. Power Down Program Sequence The program requires total 6 read/write operation with unique address and data. Between each read/write operation requires that device be in standby mode. The following table shows the detail sequence.
The first cycle is to read from most significant address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the second or third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. The fourth and fifth cycle is to write to MSB. The data of fourth and fifth cycle is don't care. If the fourth or fifth cycle is written into different address, the program is also cancelled but write data may not be wrote as normal write operation. The last cycle is to read from specific address key for mode selection. Once this program sequence is performed from a Partial mode, the write data may be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used. Address Key The address key has the following format.
Mode Sleep (default) 8M Partial A20 1 1 Address A19 A18-A0 1 1 0 1 Binary 1FFFFFh 17FFFFh
Cycle# Operation 1st Read 2nd Write 3rd Write 4th Write
Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh
Data Read Data (RDa) RDa RDa Don't Care (X)
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RECOMMENDED OPERATING CONDITIONS
Parameter Supply Voltage High Level Input Voltage Low Level Input Voltage Ambient Temperature Notes:
1. Maximum DC voltage on input and I/O pins are VDD + 0.2 V. During voltage transitions, inputs may positive overshoot to VDD + 1.0 V for periods of up to 5 ns.
Symbol VDD VSS VIH VIH VIL TA
Min. 2.7 0 0.8 VDD 0.8 VDD -0.3 -25
Max. 3.1 0 VDD + 0.2 and +3.6 VDD + 0.2 0.2 VDD 85
Unit V V V V V
C
2.
Minimum DC voltage on input or I/O pins are -0.3 V. During voltage transitions, inputs may negative overshoot VSS to -1.0 V for periods of up to 5 ns.
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PSRAM DC CHARACTERISTICS
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Level Output Low Voltage Level VDD Power Down Current
Symbol
ILI ILO VOH VOL IDDPS IDDP8 IDDS IDDS1 IDDA1 IDDA2
Test Conditions
VIN = VSS to VDD VOUT = VSS to VDD, Output Disable VDD = VDD(min), IOH = -0.5mA IOL = 1 mA VDD = VDD max., VIN = VIH or VIL, CE2 0.2V SLEEP 8M Partial
Min.
-1.0
Max.
+1.0
Unit
A A V
-1.0
+1.0
2.4
-
- - - - -
0.4 10 50 1.5 80
V A A mA A mA mA mA
VDD Standby Current
VDD = VDD max., VIN = VIH or VIL, CE1# VDD = VDD max., VIN 0.2 V or VIN VDD - 0.2 V, CE1# =CE2 VDD - 0.2V VDD = VDD max., VIN = VIH or VIL, CE1# = VIL and CE2 = VIH, IOUT = 0 mA tRC/tWC = minimum tRC/tWC = 1 s
VDD Active Current VDD Page Read Current
- - -
30 3 10
IDDA3
VDD = VDD max., VIN = VIH or VIL, CE1# = VIL and CE2 = VIH, IOUT = 0 mA, tPRC = min.
Notes: 1. All voltages are referenced to VSS. 2. DC Characteristics are measured after following POWER-UP timing. 3. IOUT depends on the output load conditions.
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PSRAM AC CHARACTERISTICS Read Operation
Value Parameter Read Cycle Time (Notes 1, 2) CE1# Access Time (Note 3) OE# Access Time (Note 3) Address Access Time (Notes 3,5) LB#/UB# Access Time (Note 3) Page Address Access Time (Notes 3,6) Page Read Cycle Time (Notes 1,6,7) Output Data Hold Time (Note 3) CE1# Low to Output Low-Z (Note 4) OE# Low to Output Low-Z (Note 4) LB#/UB# Low to Output High-Z (Note 4) CE1# High to Output High-Z (Note 3) OE# High to Output High-Z (Note 3) LB#/UB# High to Output High-Z (Note 3) Address Setup Time to CE1# Low Address Setup Time to OE# Low Address Invalid Time (Notes 5,8) Address Hold Time from CE1# High (Note 9) Address Hold Time from OE# High CE1# High Pulse Width Notes: 1. Maximum value is applicable if CE1# is kept at Low without change of address input of A3 to A20. 2. 3. 4. 5. Address should not be changed within minimum tRC. The output load 50pF. The output load 5pF. Applicable to A3 to A20 when CE1# is kept at Low. Symbol tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tCHAH tOHAH tCP Min. 65 - - - - - 25 5 5 0 0 - - - -5 10 - -5 -5 12 Max. 1000 65 40 65 30 20 1000 - - - - 20 20 20 - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
6. Applicable only to A0, A1 and A2 when CE1# is kept at Low for the page address access. 7. In case Page Read Cycle is continued with keeping CE1# stays Low, CE1# must be brought to High within 4 s. In other words, Page Read Cycle must be closed within 4 s. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. tRC (min) and tPRC (min) must be satisfied.
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PSRAM AC CHARACTERISTICS Write Operation
Value Parameter Write Cycle Time (Notes 1, 2) Address Setup Time (Note 3) CE1# Write Pulse Width (Note 3) WE# Write Pulse Width (Note 3) LB#/UB# Write Pulse Width (Note 3) LB#/UB# Byte Mask Setup Time (Note 4) LB#/UB# Byte Mask Hold Time (Note 5) CE1# Write Recovery Time (Note 6) WE# Write Recovery Time (Note 6) LB#/UB# Write Recovery Time (Note 6) Data Setup Time Data Hold Time OE# High to CE1# Low Setup Time for Write (Note 7) OE# High to Address Setup Time for Write (Note 8) WE#/UB#/LB# High to OE# Low Setup Time for Read (Note 10) LB# and UB# Write Pulse Overlap CE1# High Pulse Width Address Hold Time for Write End (Note 3) Notes: 1. Maximum value is applicable if CE1# is kept at Low without any address change. 2. Minimum value must be equal or greater than the sum of write pulse (tCW, TWP, TBW) and write recovery time (tWCR, TWR or tBR). 3. Write pulse is defined from High to Low transition of CE1#, WE#, or LB#/UB#, whichever occurs last. 4. Applicable for byte mask only. Byte mask setup time is defined to the High to Low transition of CE1# or WE# whichever occurs last. 5. Applicable for byte mask only. Byte mask hold time is defined from the Low to High transition of CE1# or WE# whichever occurs first. 6. Write recovery is defined from Low to High transition of CE1#, WE#, or LB#/UB#, whichever occurs first. Symbol tWC tAS tCW tWP tBW tBS tBH tWRC tWR tBR tDS tDH tOHCL tOES tWHOL tBWO tCP tAH Min. 65 0 40 40 40 -5 -5 12 7.5 12 12 0 -5 0 12 30 12 0 Max. 1000 - - - - - - - 1000 1000 - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns ns ns
7. If OE# is Low after minimum tOHCL, read cycle is initiated. In other words, OE# must be brought to High within 5 ns after CE1# is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met 8. If OE# is Low after new address input, read cycle is initiated. In other words, OE# must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met and data bus is in High-Z 9. Absolute minimum values and defined at minimum VIH level. 10. If the actual value of tWHOL is shorter than the specified minimum values, the actual tAA of following Read may become longer by the amount of subtracting the actual value from the specified minimum value.
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AC CHARACTERISTICS Power Down Parameters
Value Parameter CE2 Low Setup Time for Power Down Entry CE2 Low Hold Time after Power Down Entry CE1# High Hold Time following CE2 High after Power Down Exit (SLEEP mode only) (Note 1) CE1# High Hold Time following CE2 High after Power Down Exit (not in SLEEP mode) (Note 2) CE1# High Setup Time following CE2 High after Power Down Exit (Note 1) Notes: 1. Applicable also to power up. Symbol tCSP tC2LP tCHH tCHHP tCHS Min. 10 65 300 1 0 Max. - - - - - Unit ns ns
s s
ns
2. Applicable when 8M Partial mode is programmed.
Other Timing Parameters
Value Parameter CE#1 High to OE# Invalid Time for Standby Entry CE#1 High to WE# Invalid Time for Standby Entry (Note 1) CE2 Low Hold Time after Power up CE1# High Hold Time following CE2 High after Power up Input Transition Time (Note 2) Notes: 1. Some data might be written into any address location if tCHWX (min) is not satisfied Symbol tCHOX tCHWX tC2LH tCHH tT Min. 10 10 50 300 1 Max. - - 25 Unit ns ns
s s
ns
2. The Input Transition Time (tT) at AC testing is 5ns, as shown in AC Test Conditions below... If actual tT is longer than 5ns, it may violate AC specification of some timing parameters.
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AC CHARACTERISTICS AC Test Conditions
Symbol VIH VIL VREF tT Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Test Setup 15, 11 VDD * 0.8 VDD * 0.2 VDD * 0.5 5 Unit V V V ns
Between VIL and VIH
VDD 0.1 F VSS DEVICE UNDER TEST 50pF OUT
Figure 26.
AC Measurement Output Load Circuit
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TIMING DIAGRAMS
tRC ADDRESS tASC CE1# tOE OE# tOHZ tBA LB / UB# tBLZ tOLZ DQ (Output) tCLZ tOH tBHZ ADDRESS VALID tCHAH tASC
tCE
tCP tCHZ
VALID DATA OUTPUT
Note: CE2 and WE# must be High for entire read cycle.
Figure 27.
Read TIming #1 (Basic Timing)
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tRC ADDRESS ADDRESS VALID tAA CE1#
tAx
tRC ADDRESS VALID tAA tOHAH
Low
tASO OE#
tOE
LB / UB# tOHZ tOLZ DQ (Output) VALID DATA OUTPUT VALID DATA OUTPUT tOH tOH
Note: CE2 and WE# must be High for entire read cycle.
Figure 28.
Read Timing #2 (OE# and Address Access)
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TIMING DIAGRAMS
tAX ADDRESS tAA CE1#,OE# tRC ADDRESS VALID tAx
Low tBA
tBA LB#
tBA UB# tBHZ tBLZ DQ0-DQ7 (Output) VALID DATA OUTPUT DQ8-DQ15 (Output) VALID DATA OUTPUT VALID DATA OUTPUT tBLZ tBHZ tOH tOH tBLZ tBHZ tOH
Note: CE2 and WE# must be High for entire read cycle.
Figure 29.
Read Timing #3 (LB#/UB# Byte Access)
tRC
ADDRESS (A20-A3) tRC ADDRESS (A2-A0) tASC CE1# tCE ADDRESS VALID
ADDRESS VALID tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPRC
ADDRESS VALID
tPAA
tPAA
tPAA
tCHAH
tCHZ
OE#
LB# / UB# tOH tOH tOH tOH
tCLZ DQ (Output)
VALID DATA OUTPUT (Normal Access)
VALID DATA OUTPUT (Page Access)
Note:CE2 and WE# must be High for entire read cycle.
Figure 30.
Read Timing #4 (Page Access after CE1# Control Access)
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TIMING DIAGRAMS
tRC ADDRESS (A20-A3) ADDRESS VALID tRC ADDRESS (A2-A0)
ADDRESS VALID
tAX
tRC ADDRESS VALID
tAx
tPRC
ADDRESS VALID
tRC
ADDRESS VALID
tPRC
ADDRESS VALID
tAA CE1#
tPAA
tAA
tPAA
Low tASO tOE
OE#
tBA LB# / UB# tOLZ tBLZ tOH tOH tOH tOH
DQ (Output)
VALID DATA OUTPUT (Normal Access)
VALID DATA OUTPUT (Page Access)
Note: CE2 and WE# must be High for entire read cycle. Either or both LB# and UB# must be Low when both CE1# and OE# are Low.
Figure 31.
Read Timing #5 (Random and Page Address Access)
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TIMING DIAGRAMS
tWC ADDRESS tAS CE1# tAS WE# tAS LB #, UB# tOHCL OE# tDS DQ (Input) VALID DATA INPUT tDH tBR tAS tWR tAS tBW ADDRESS VALID tAH tAS
tCW
tWP
Note: CE2 must be High for Write Cycle.
Figure 32.
tWC ADDRESS
Write Timing #1 (Basic Timing)
tWC ADDRESS VALID
ADDRESS VALID
tOHAH CE1# Low tAS WE# tWR tWP tAH tAS tWP tWR
LB#, UB# tOES OE# tOHZ DQ (Input) VALID DATA INPUT VALID DATA INPUT tDS tDH tDS tDH
Note: CE2 must be High for Write Cycle.
Figure 33. June 17, 2004
Write Timing #2 (WE# Control) Am49LV128BM 67
TIMING DIAGRAMS
tWC ADDRESS ADDRESS VALID tWC ADDRESS VALID
CE1#
Low tWR tWR
WE# tAS LB# tBS UB# tDS DQ0-DQ8 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBW tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 34.
Write Timing #3-1 (WE#/LB#/UB# Byte Write Control)
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tWC ADDRESS ADDRESS VALID
tWC ADDRESS VALID
CE1#
Low t WR tWR
WE# tAS LB# tBS UB# tDS DQ0-DQ7 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBW tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 35.
Write Timing #3-2 (WE#/LB#/UB# Byte Write Control)
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TIMING DIAGRAMS
tWC ADDRESS ADDRESS VALID tWC ADDRESS VALID
CE1#
Low
WE# tAS LB# tBS UB# tDS DQ0-DQ7 (Input) VALID DATA INPUT DQ8-DQ15 (Input) VALID DATA INPUT tDS tDH tDH tBH tAS tBW tBR tBW tBR tBS tBH
Note: CE2 must be High for Write Cycle.
Figure 36.
Write Timing #3-3 (WE#/LB#/UB# Byte Write Control)
tWC tWC ADDRESS VALID
ADDRESS
ADDRESS VALID
CE1#
Low
WE# tAS LB# tBWO tDS DQ0-DQ7 (Input) tAS UB# tDS DQ8-DQ15 (Input) tDH tDS tDH tDH tDS tDH tBW tBR tAS tBW tBR
VALID DATA INPUT
VALID DATA INPUT
tBW
tBR
tAS
tBWO tBW
tBR
VALID DATA INPUT
VALID DATA INPUT
Note: CE2 must be High for Write Cycle.
Figure 37.
Write Timing #3-4 (WE#/LB#/UB# Byte Write Control)
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TIMING DIAGRAMS
tWC ADDRESS tCHAH CE1# tCP tCP tAS WRITE ADDRESS tWRC tCW tASC tRC READ ADDRESS tCHAH
tCE
WE#
UB#,LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tCLZ tOH
Note: Write address is valid from either CE1# or WE# of last falling edge.
Figure 38.
Read/Write Timing #1-1 (CE1# Control)
tWC tRC READ ADDRESS tWR tASC tCHAH
ADDRESS tCHAH CE1# tCP tAS
WRITE ADDRESS
tCE
tCP tWP
WE#
UB#,LB# tOHCL OE# tCHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tOLZ tOH
tOE
Note: OE# can be fixed Low during write operation if it is CE1# controlled write at Read-Write-Read sequence.
Figure 39.
Read/Write Timing #1-2 (CE1#/WE#/OE# Control)
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TIMING DIAGRAMS
tWC ADDRESS WRITE ADDRESS tRC READ ADDRESS tAA tOHAH CE1# Low tAS WE# tOES tWP tWR tOHAH
UB#,LB#
tASO OE# tOHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT tDS tDH tOLZ
tOE
tOHZ tOH
READ DATA OUTPUT
Note: CE1# can be tied to Low for WE# and OE# controlled operation.
Figure 40.
Read/Write Timing #2 (OE#, WE# Control)
tWC tRC READ ADDRESS tAA
ADDRESS
WRITE ADDRESS
tOHAH CE1# Low
tOHAH
WE# tOES UB#,LB# tBHZ OE# tBHZ tOH DQ READ DATA OUTPUT WRITE DATA INPUT READ DATA OUTPUT tDS tDH tBLZ tOH tASO tAS tBW tBR
tBA
Note: CE#1 can be tied to Low for WE# and OE# controlled operation.
Figure 41.
Read/Write Timing #3 (OE#, WE#, LB#, UB# Control)
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TIMING DIAGRAMS
CE1# tCHS tC2LH CE2 tCHH
VDD
0V
VDD min
Note: The tC2LH specifies after VDD reaches specified minimum level.
Figure 42.
Power-up Timing #1
CE1# tCHH CE2
VDD
0V
VDD min
Note: The tCHH specifies after VDD reaches specified minimum level and applicable to both CE1# and CE2.
Figure 43.
Power-up Timing #2
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TIMING DIAGRAMS
CE1# tCHS CE2 tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Note: This Power Down mode can be also used as a reset timing if Power-up timing above could not be satisfied and PowerDown program was not performed prior to this reset.
Figure 44.
CE1# tCHOX OE#
Power-down Entry and Exit Timing
tCHWX
WE# Active (Read) Standby Active (Write) Standby
Note: Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (min) period for standby mode from CE1# Low to High transition.
Figure 45.
Standby Entry Timing after Read or Write
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TIMING DIAGRAMS
tRC ADDRESS MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tWC MSB*1 tRC Key*2
tCP CE1#
tCP
tCP
tCP
tCP
tCP*3
OE#
WE#
LB#,UB#
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
X Cycle #4
X Cycle #5
RDb Cycle #6
Notes:
1. The all address inputs must be High from Cycle #1 to #5.
2.
After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
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AM49LV128BM MCP WITH SECOND PSRAM SUPPLIER PSRAM BLOCK DIAGRAM
Note: ZZ# = CE2pS on MCP pin-out.
FUNCTION TRUTH TABLE
Mode Standby (Note 2) Standby (Note 2) Write Read Active Deep Sleep Note:
1. When UB# and LB# are in select mode (low), I/O 0 - I/O15 are affected as shown. When LB# only is in the select mode only I/O0 - I/ O7 are affected as shown. When UB# is in the select mode only I/O8 - I/O15 are affected as shown.
CE# H X L L L X
ZZ# H H H H H L
WE# X X L H H X
OE# UB# LB# X X X X H H X (Note 3) L (Note 1) L (Note 1) L L (Note 1) L (Note 1) H L L X X X
I/O0 - I/O15 (Note1) High-Z High-Z Data In Data Out High-Z High-Z
POWER Standby Standby Active Active Active Deep Sleep
internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
2.
When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB#), address inputs and data input/outputs are
ABSOLUTE MAXIMUM RATINGS (NOTE 1)
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Note:
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol VIN,OUT VCC PD TSTG TA
Rating -0.2 to VCC+0.3 -0.2 to 3.6 1 -40 to 125 -25 to +85
Unit V V W oC oC
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OPERATING CHARACTERISTICS (OVER SPECIFIED TEMPERATURE RANGE)
Item Symbol Supply Voltage VCC Supply Voltage for I/O VCCQ Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH Output Low Voltage VOL Input Leakage Current ILI Output Leakage Current ILO Read/Write Operating Supply Current ICC1 @1 s Cycle Time (Note 2) Read/Write Operating Supply Current ICC2 @65 ns Cycle Time (Note 2) Page Mode Operating Supply Current ICC2 @65 ns Cycle Time (Note 2) Maximum Standby Current (Note 3) Note:
1. Typical values are measured at Vcc=Vcc Typ., TA=25C and not 100% tested.
Test Condition
ISB1
IOH = 0.5mA IOL = -0.5mA VIN = 0 to VCC OE# = VIH or Chip Disabled VCC= 3.1V, VIN=CMOS levelsChip Enabled, IOUT = 0 VCC= 3.1V, VIN=CMOS levels Chip Enabled, IOUT = 0 VCC= 3.1V, VIN=CMOS levels Chip Enabled, IOUT = 0 VCC= 3.1V, VIN=CMOS levels Chip Disabled
3.
Typ Min (Note 1) 2.7 3.0 2.7 3.0 0.8VCCQ -0.2 0.8VCCQ -1 -1
Max 3.1 VCC VCCQ+0.2 0.2VCCQ 0.2VCCQ 1 1 3.0 25.0 25.0
Unit V V V V V V A A mA mA mA A
80
120
2.
This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system.
This device assumes a standby mode if the chip is disabled (either CE# high or both UB# and LB# high). In order to achieve low standby current all inputs must be within 0.2V of either VCC or VSS.
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OUTPUT LOAD CIRCUIT
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TIMING
65ns Item Read Cycle Time Address Access Time Page Mode Read Cycle Time Page Mode Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Page Mode Write Cycle Time Page Mode CE Precharge Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Write Precharge Time Address Setup Time Write Recovery Time Write to High-Z Output Data to Write Time Overlap Page Mode Data to Write Time Overlap Data Hold from Write Time Page Mode Data Hold from Write Time End Write to Low-Z Output Maximum Page Mode Cycle Symbol tRC tAA tPC tPA tCO tOE tLB, tUB tLZ tOLZ tLBZ, tUBZ tHZ tOHZ tLBHZ, tUBHZ tOH tWC tPWC tCP tCW tAW tLBW, tUBW tWP tWEH tAS tWR tWHZ tDW tPDW tDH tPDH tOW tPGMAX Min. 65 25 Max. 65 20000 25 65 20 65 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10 5 10 0 0 0 5 65 25 10 55 55 55 50 7.5 0 0 25 20 0 0 5
5 5 5
20000
20000
5
20000
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TIMING OF READ CYCLE (CE# = OE# = VIL, WE# = VIH)
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TIMING WAVEFORM OF READ CYCLE (WE#=VIH)
Address
CE#
OE#
LB#,UB#
Data Out
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TIMING WAVEFORM OF PAGE MODE READ CYCLE (WE# = VIH)
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TIMING WAVEFORM OF WRITE CYCLE (WE# CONTROL)
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TIMING WAVEFORM OF WRITE CYCLE (CE# CONTROL)
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TIMING WAVEFORM FOR SUCCESSIVE WE# WRITE CYCLES
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TIMING WAVEFORM OF PAGE MODE WRITE CYCLE
POWER SAVINGS MODES
The PSRAM has three power savings modes: Reduced Memory Size Partial Array Refresh Deep Sleep Mode The operation of the power saving modes is controlled by setting the Variable Address Register (VAR). This VAR is used to enable/disable the various low power modes. The VAR is set by using the timings. The register must be set in less then 1s after ZZ# is enabled low.
mains active until the register is updated. To return to the full 32Mb address space, the VA register must be reset using the previously defined procedures.
Partial Array Refresh (PAR)
In this mode, the internal refresh operation can be restricted to a 8Mb, 16Mb or 24Mb portion of the array. The mode and array partition to be refreshed are determined by the settings in the VAR register. The VAR register is set according to the timings and the bit settings. In this mode, when ZZ# is taken low, only the portion of the array that is set in the register is refreshed. The operating mode is only available during standby time and once ZZ# is returned high, the device resumes full array refresh. All future PAR cycles will use the contents of the VA register. To change the address space of the PAR mode, the VA register must be reset using the previously defined procedures. The default state for the ZZ# register will be such that ZZ# low will put the device into PAR mode after 1s and never initiate a deep sleep mode unless appropri-
Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb, 16Mb or a 24Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the timings and the bit settings. The RMS mode is enabled at the time of ZZ# transitioning high and the mode re-
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ate register is updated. This device is referred to as Deep Sleep Inactive, or DSI device. In either device, once the SRAM enters Deep Sleep Mode, the VAR contents are destroyed and the default register settings are reset.
Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ# low. After 1 s, if the VAR register corresponding to A4 is not set to Deep Sleep Disabled, the device will enter Deep Sleep Mode. The device will remain in this mode as long as ZZ# remains low.
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VARIABLE ADDRESS REGISTER
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VARIABLE ADDRESS REGISTER (VAR) UPDATE TIMINGS
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DEEP SLEEP MODE - ENTRY/EXIT TIMINGS
VAR UPDATE AND DEEP SLEEP TIMINGS
Item PAR and RMS ZZ# low to WE# low Chip (CE#, UB#/LB#) deselect to ZZ# low Deep Sleep Mode Deep Sleep Recovery Symbol tzzwe tcdzz tzzmin tr Min 0 10 200 Max 1000 Unit ns ns ns ns
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ADDRESS PATTERNS FOR PAR (A3 = 0, A4 = 1)
A2 0 0 x 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full Die One-quarter of die One-half of die Address Space Size 000000h - 07FFFFh 512Kb x 16 000000h - 0FFFFFh 1Mb x 16 000000h-1FFFFFh 2Mbx16 180000h - 1FFFFFh 512Kb x 16 100000h - 1FFFFFh 1Mb x 16 Density 8Mb 16Mb 32Mb 8Mb 16Mb
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ADDRESS PATTERNS FOR RMS (A3 = 1, A4 = 1)
A2 0 0 X 1 1 A1 1 1 0 1 1 A0 1 0 0 1 0 Active Section One-quarter of die One-half of die Full die One-quarter of die One-half of die Address Space Size 000000h - 07FFFFh 512Kb x 16 000000h - 0FFFFFh 1Mb x 16 000000h - 1FFFFFh 2Mb x 16 180000h - 1FFFFFh 512Kb x 16 100000h - 1FFFFFh 1Mb x 16 Density 8Mb 16Mb 32Mb 8Mb 16Mb
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LOW POWER ICC CHARACTERISTICS FOR PSRAM
Item PAR Mode Standby Current RMS Mode Standby Current Deep Sleep Current Symbol IPAR IRMSSB IZZ Test VIN = VCC or 0V, Chip Disabled, tA= 85C VIN = VCC or 0V, Chip Disabled, tA= 85C VIN = VCC or 0V, Chip in ZZ# mode, tA= 85C Array Partition 1/4 Array 1/2 Array 8Mb Device 16Mb Device Typ 50 70 50 70 7 Max 75 90 75 90 10 Unit A A A
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PHYSICAL DIMENSIONS TLD064-64-Ball Fine-pitch Ball Grid Array
D
0.15 C (2X)
10 9 8 7 6 5 4
A
D1 eD
SE 7 E1
E eE
3 2 1
INDEX MARK PIN A1 CORNER 10
MLKJ
HG F
EDC
BA
B
7
TOP VIEW
0.15 C (2X)
SD
PIN A1 CORNER
BOTTOM VIEW A A2 A1
6
0.20 C
C
0.08 C
SIDE VIEW b
M CAB MC
64X
0.15 0.08
PACKAGE JEDEC DxE SYMBOL A A1 A2 D E D1 E1 MD ME n b eE eD SD / SE 0.35
TLD 064 N/A 12.00 mm x 9.00 mm PACKAGE MIN --0.10 0.81 NOM ------12.00 BSC. 9.00 BSC. 8.80 BSC. 7.20 BSC. 12 10 64 --0.80 BSC. 0.80 BSC 0.40 BSC. 0.45 MAX 1.20 --0.97 PROFILE BALL HEIGHT BODY THICKNESS BODY SIZE BODY SIZE MATRIX FOOTPRINT MATRIX FOOTPRINT MATRIX SIZE D DIRECTION MATRIX SIZE E DIRECTION BALL COUNT BALL DIAMETER BALL PITCH BALL PITCH SOLDER BALL PLACEMENT NOTE
NOTES: 1. 2. 3. 4. 5. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. e REPRESENTS THE SOLDER BALL GRID PITCH. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 7 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. N/A
A2,A3,A4,A5,A6,A7,A8,A9 DEPOPULATED SOLDER BALLS B1,B2,B3,B4,B7,B8,B9,B10 C1,C2,C9,C10,D1,D10,E1,E10 F1,F5,F6,F10,G1,G5,G6,G10 H1,H10,J1,J10,K1,K2,K9,K10 L1,L2,L3,L4,L7,L8,L9,L10 M2,M3,M4,M5,M6,M7,M8,M9
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3309 \ 16-038.22a
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REVISION SUMMARY Revision A (January 22, 2004)
Initial release.
Revision A+4 (March 4, 2004)
Lookahead Diagram Added the lookahead diagram.
Revision A+1 (January 29, 2004)
Connection Diagrams Corrected signal designation on ball H8. AC Characteristics (Flash) Read-only Operations: Added Figure 14. pSRAM AC Characteristics Figure 32, Write Timing #1 (Basic Timing): Renamed tWRC to tAH; extended tWR to where WE# returns low; extended tBR to where LB#, UB# goes low. Figure 33, Write Timing #2 (WE# Control): The period along WE# formerly labeled tWR is now tAH. A new tWR period has been added which extends from WE# going high after the first tWP period to where the second tWP period begins. Figure 34, Write Timing #3-1 (WE#/LB#/UB# Byte Write Control): tWR has been extended to where WE# returns low. Figure 35, Write Timing #3-2 (WE#/LB#/UB# Byte Write Control): tWR has been extended to where WE# returns low. Write Operations table: Changed minimum specification for tWR from 12 to 7.5 ns. Added tAH specification.
Revision A+5 (March 15, 2004)
Global Changed DQ designations to 0-7 and 8-15. Global Removed references to the 4M Partial power down mode and added references to Deep Sleep. Recommended Operating Conditions Corrected Min. and Max values for VIH parameter. PSRAM AC Characteristics Write Operation Changed column head to Value, added tWHOL parameter, changed min value of t BWO to 30, and added Notes 8, 9, and 10. AC Characteristics Added Power Down Parameters and Other Timing Parameters tables. AM49LV128BM MCP with Second PSRAM Supplier Removed Capacitance section. Partial Array Refresh (PAR) Removed reference to two versions.
Revision A+2 (February 16, 2004)
PSRAM Features Feature list was corrected to four main features Lookahead Pinout Diagram Figure was removed and replaced by TBD. Ordering Information Added and option that designates standard or second supplier for PSRAM. AM49LV128BM MCP with Second Supplier Section added.
Revision A6 (June 17, 2004)
"Absolute Maximum Ratings" on page 37 Changed "Voltage on VCC Supply relative to VSS Rating" To -0.2 to 3.6. Changed "Power Dissipation - Rating" to 1. Changed "Operating Temperature - Rating" to -25 to +85. "Low Power ICC Characteristics for PSRAM" on page 93 Changed "PAR Mode Standby Current" - Type to "50" and Max to "75". Changed "RMS Mode Standby Current - 8Mb Device" - Type to "50" and Max to "75". Changed "RMS Mode Standby Current - 16Mb Device" - Type to "70" and Max to "90". Changed "Deep Sleep Current" -Type to "7". "Address Patterns for RMS (A3 = 1, A4 = 1)" on page 92 Deleted "Three-quarters of die from table.
Revision A+3 (February 25, 2004)
Operating Ranges Removed VIO from the list of supply voltages. AM49LVxxxBM MCP with Second Supplier PSRAM Block Diagram Added a note clarifying ZZ#.
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Deleted "Full Die" from table. "Address Patterns for PAR (A3 = 0, A4 = 1)" on page 91 Added "Full Die" to table. "Timing" on page 79 Changed "Chip Disable to High-Z Output - Max" to 5. Changed "Output Disable to High-Z Output - Max" to 5. Changed "Byte Select Disable to High-Z Output - Max" to 5. Changed "Write to High-Z Output - Max" to 5. "Operating Characteristics (Over Specified Temperature Range)" on page 77 Changed "Supply Voltage for I/O - Min" to 7.7. Changed "Input High Voltage - Min" to 0.8. Changed "Output High Voltage - Max" to 0.2.
Changed "Output Low Voltage - Test Condition" to...=0.5mA.hanged "Output Low Voltage - Max." to 0.2VccQ. Changed "Input Leakage Current - Min." to -1. Changed "Input Leakage Current - Max." to 1. Changed "Output Leakage Current - Min." to -1 Changed "Output Leakage Current - Max." to 1. Changed "Read/Write Operating Supply Current @1...-Test Condition" to Vcc=3.1V... Changed "Read/Write Operating Supply Current @65...-Test Condition" to Vcc=3.1V... Changed "Page Mode Operating Supply Current. Test Condition" to Vcc=3.1V... Changed "Page Mode Operating Supply Current. Max." to 25.0 Changed "Maximum Standby Current - Test Condition" to Vcc=3.1V... Changed "Maximum Standby Current - Max." to 120.
Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that FASL will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks Copyright (c) 2003-2004 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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